FIG. 1 shows a conventional PC AT (registered IBM trademark) computer system consisting of a central processing unit ("CPU"), a system bus, a system memory, a memory controller, an Industrial Standard Architecture ("ISA") AT bus, an ISA AT bus controller and peripheral devices. The system bus which transmits data, address and control signals, is a high speed bus connecting the CPU, system memory, and other controllers together. The ISA AT bus is defined to have a 16-bit data bus, a 24-bit address bus, and control signals as well as input/output ("IO") port addresses assigned for various types of peripherals. For instance, IO port address 1F0H is assigned as the data port address of one or two primary hard disk drives, and IO port address 170H is assigned as the data port address of one or two secondary hard disk drives. FIG. 1 illustrates one such hard disk drive.
The system bus normally runs at a considerably higher clock rate than the ISA AT bus. For a 33-MHz 386 PC AT system, the system bus runs at 33 MHz while the ISA AT bus runs at 6 to 8 MHz.
The ISA AT bus controller, sitting between the system bus and the ISA AT bus, transmits data, address and control signals between the system bus and the ISA AT bus so that the CPU can perform operations on peripheral devices, such as a hard disk or a display monitor, through a peripheral controller, such as an Integrated Device Electronics ("IDE") controller and/or a graphics display controller. The peripheral device controller can be either assembled on a printed-circuit-board ("PCB"), referred to as the main board, with the CPU and memory subsystem or plugged into one of several 8-bit or 16-bit expansion slots generally available on the main board.
To allow storage peripherals to be attached to the ISA AT bus, the American National Standard for Information Systems ("ANSIS") AT Attachment ("ATA") specification defines a compatible register set and a 40-pin connector, including its associated signals. For example, an IDE interface hard disk drive strictly follows the bus interface requirements defined in the ANSIS ATA. Therefore, the IDE hard drive can be attached to the ISA AT bus.
A hard disk drive contains one or more disk plates. Each of disk plates is formatted into tracks and sectors. The number of tracks on a disk plate can vary from drive to drive, though the size of a sector is defined to be 512 bytes of data.
Each hard disk drive normally contains registers to receive commands from the CPU, and a data register for the CPU to retrieve data from the hard drive or store data into the hard drive. The AT specification assigns 1F0H as the address of the data register in each primary hard drive, and 170H as the address of the data register in each secondary hard drive.
In a PC AT computer system which uses an IDE hard disk drive for data storage, a conventional ISA IO control chip, such as the FDC37C6xx series of Standard Microsystems, the PC873xx series of National Semiconductor, the W83757 of Winbond Electronics, or the ALI M5107 of Acer Lab., can be used to control the IDE hard drive.
To read data from the IDE hard drive and write the data into the system memory, the CPU first issues a disk read command and passes a sector number to the hard disk through the ISA AT bus controller and the IDE hard drive controller. The IDE hard drive, having been informed of the disk read command and sector number, moves data from the hard disk sector into the sector buffer of the IDE hard drive for the CPU to access. The CPU then executes a 16-bit IO instruction to input data from IO port 1F0H or 170H. The ISA IO controller decodes the IO address and activates the hard drive to output 16-bit data to the ISA AT bus. The ISA AT bus controller then moves the data from the ISA AT bus to the system bus. In the same instruction cycle, the CPU stores the data received from the system bus into the system memory. This completes a 16-bit hard disk data read operation.
FIG. 2 shows signal waveforms of 16-bit hard drive data read operations for a PC AT system with a 33 MHz CPU clock and an 8 MHz AT bus clock. The CPU first places IO port address 1F0H or 170H on the system address bus, activates the address strobe signal ADS.sub.--, and drives the memory/IO cycle indicating signal MIO.sub.-- low to initiate an IO cycle. The underline (.sub.--) at the end of a signal, such as the ADS.sub.-- or MIO.sub.-- signal, indicates that it is active low.
The activated ADS.sub.-- signal triggers the ISA AT bus controller to forward the IO port address to the AT bus and activate the address latch signal ALE of the AT bus for the IDE controller to latch and decode the IO port address. The ALE signal is deactivated by the end of the first AT clock cycle. The AT bus controller then enables the IO read signal IOR.sub.--, which triggers the hard drive to output data to the AT bus. The IOR.sub.-- signal is deactivated by the end of the third AT clock cycle if the IDE hard drive does not assert an IO channel-ready signal (not shown) to request longer response time. The IDE data is moved from the AT bus to the system bus by the AT bus controller. It then asserts the data ready signal RDY.sub.-- for the CPU to latch the data and finish the IO read cycle.
After the IO read cycle, the CPU places the memory address and the latched hard disk data on the system bus, activates the strobe signal ADS.sub.--, and drives both the MIO.sub.-- signal and the write/read indicating signal WR.sub.-- high to generate a memory write cycle for storing the hard disk data into the system memory. This completes a 16-bit "read hard disk, write memory" operation.
As shown in FIG. 2, the CPU generates 16-bit IO read and memory write cycles one after the other. Since 16 bits is 2 bytes, to move a whole sector--i.e. 512 bytes--of data from the hard drive to the system memory, the 16-bit AT IO read and memory write cycles must be repeated 256 times. In between the 16-bit data transfer operations, "back to back AT IO cycle delay" may be needed to ensure compatibility with slow hard drive. The use of "back to back AT IO cycle delay" in between 16-bit data transfers increases the data transfer cycle time and slows down the data transfer rate.
In an Intel i3/486-based computer system, 16-bit IO instruction REP INS is commonly used in the Basic Input and Output System ("BIOS") to move data from the hard drive's IO data port to the system memory. The REP INS instruction repeatedly performs "input data from IO port, then write the input data to memory" operations until a designated loop count is reached. For each REP INS loop, one 16-bit AT IO read cycle is needed to input data from the IDE drive, and 6 CPU clocks are needed to store the IDE data into the system memory and prepare for the next loop to start. FIG. 2 shows that the 16-bit AT IO read cycle requires at least 3 AT bus clocks to finish.
For a 33-MHz Intel i486-based system with an 8-MHz AT bus clock, 30 ns and 120 ns respectively are the approximate durations for the CPU clock and the AT clock. Therefore, it takes at least (6.times.30 ns)+(120.times.3)=540 ns to complete a 16-bit data read transfer from the hard drive to the system memory. This translates into a maximum data transfer rate of 3.7 megabytes per second, assuming that no "back to back AT IO cycle delay" is required by the hard drive and that the data is always available for the CPU to access on the hard drive.
To read data from the system memory and write the data into the hard disk drive, the CPU first executes an IO output instruction that causes a command to be issued, via the ISA AT bus controller and the hard drive controller, to the hard drive to request a sector buffer. When the hard drive is ready to receive data, the CPU generates a memory read cycle to read data from the system memory. The CPU then generates a 16-bit IO write cycle to write the data into the hard disk data port. The ISA IO controller decodes the IO port address, and moves data from the system bus into the sector buffer of the hard drive via the AT bus. This completes a 16-bit hard drive data write operation.
FIG. 3 shows signal waveforms of 16-bit hard drive data write operations for a PC AT system with a 33-MHz CPU clock and an 8-MHz AT bus clock. The CPU first reads data from the system memory by outputting the memory address to the system bus and activating address strobe signal ADS.sub.--. The ready signal RDY.sub.-- is then asserted by the memory controller to inform the CPU that memory data is ready to latch. When the memory data is fetched into the CPU, it starts an IO write cycle by asserting IO port address 1F0H or 170H on the system address bus, generating the ADS.sub.-- signal and IO cycle indicating signal MIO.sub.-- followed by outputting the latched data onto the system data bus. These signals trigger the AT bus controller to forward the IO port address to the AT bus, and supply address latch signal ALE to the hard disk controller by the end of the first AT clock.
The hard disk controller, triggered by the activated ALE signal, decodes the IO port address and prepares to receive data from the AT bus controller. Data is then routed from the system bus to the AT bus, and the IO write signal IOW.sub.-- is activated in the middle of the 2nd AT clock by the AT bus controller. The IOW.sub.-- signal is deactivated by the end of the third AT clock if the hard drive does not assert the IO channel-ready signal (not shown) to request longer response time. The RDY.sub.-- signal is then activated to indicate the end of the IO write operation.
As shown in FIG. 3, the CPU must generate memory read and 16-bit IO write cycles one after the other to fetch data from the system memory and store it into the hard disk's data port. To move a whole sector--i.e. 512 bytes--of data from the system memory to the hard drive, the 16-bit memory read and AT IO write cycles must be repeated 256 times. In between the 16-bit data transfer operations, "back to back AT IO cycle delay" may be needed to ensure compatibility with slow hard disk drive. The use of "back to back AT IO cycle delay" in between 16-bit data transfers again increases the data transfer cycle time and slows down the data transfer rate.
In an Intel i3/486-based computer system, 16-bit IO instruction REP OUTS is commonly used in the BIOS to move data from the system memory to the hard disk. The REP OUTS instruction repeatedly performs "read data from the system memory, and write the data into a designated IO port" operations until a designated loop count is reached. For each REP OUTS loop, according to Intel's published data, one 16-bit AT IO write cycle is needed to output data to the IO port, and 5 CPU clocks are needed to read data from the system memory and prepare for the next loop to start. FIG. 3 shows that a 16-bit AT IO write cycle requires at least 3 AT clocks to finish.
For a 33-MHz Intel i486-based system with an 8-MHz AT bus clock, it takes at least (5.times.30 ns)+(120.times.3)=510 ns to complete a 16-bit data write transfer to the hard drive. This translates into a maximum data transfer rate of 3.9 megabytes per second if no "back to back AT IO cycle delay" is required by the hard drive.